Pulse width discriminator applicable to ATC transponders

ABSTRACT

A pulse width discriminating circuit and technique is disclosed which enables the rejection of pulses having a width less than and greater than predetermined limits. A received pulse is provided as one input to a counting circuit which is driven by a clock to provide count outputs as long as an input pulse is present. The counter has an output selected to indicate when the width of the pulse has exceeded a minimum time, and an output selected to indicate when the width of the pulse has exceeded a maximum time. The minimum pulse width output signal controls the entry of a pulse in a shift register. The shift register is shifted by a divided clock signal from the same clock that drives the counter and provides an output to a decoding circuit after a predetermined time if the pulse width falls within the predetermined range. The maximum pulse width output signal is coupled to reset the shift register so that the pulse in the shift register is discarded if the input pulse exceeds a predetermined width.

BACKGROUND OF THE INVENTION

The present invention relates to digital signal detecting circuitry and more particularly to a digital circuit which enables pulse width discrimination.

In a variety of electronic systems, information transmission and reception is often accomplished and controlled by the generation of pulses representing digital information. The pulses may be of a variety of configurations and may include modulation of their width, height and repetition frequency in order to convey certain information. Naturally, in any such system, the accuracy of the information transmitted is dependent upon the effective detection of the pulses so that unwanted or spurious signals may be separated from the transmitted pulses.

In one technique of transmitting information by digital pulses, the width of the transmitted pulses is fixed within predetermined limits so that the pulse may be distinguished from other signals. In this instance, if an unwanted signal of any magnitude, repetition or duration is received from a spurious source, it may be easily distinguished if its duration falls outside of the predetermined limits. By way of example, pulse width detection is used in aircraft transponders wherein the timing of a series of transmitted pulses is intended to elicit particular information from an aircraft. As can be appreciated, when such timing is critical to determining the mode of aircraft response, it is important that unwanted pulses are not detected as interrogation pulses so that they interfere with the interrogation timing sequence.

In the prior art, pulse width discrimination in transponder and other aircraft system has been generally accomplished by employing lumped delay lines and analog delays. Lumped delay lines, however, are bulky and cannot be easily used with the miniaturized digital circuits employed in new technology aircraft. Analog delay circuits are also bulky and suffer from additional deficiencies. Specifically, analog delays have a tendency to drift and require frequent adjustment in order to maintain the precise delay times needed for enabling pulse width discrimination. Neither of these techniques, are capable of providing the fixed, stable and reproducible delay times needed for distinguishing critical pulse widths. There is therefore a continuing need for digital circuitry which can provide such reproducible characteristics and enable pulse width detection and discrimination in a variety of digital circuits.

Accordingly, the present invention has been developed to overcome the shortcomings of the above known and similar techniques, and more particularly, to provide a digital pulse width discriminator for accurately detecting pulse width within precisely defined limits.

SUMMARY OF THE INVENTION

In accordance with the present invention, the discriminator circuit includes a counter having one input for receiving a train of transmitted pulses, an input clocked by a stable clocking circuit and outputs representing specifically timed counts. One output of the counter provides a minimum count signal when an input pulse width exceeds a predetermined minimum time period and another output of the counter provides a maximum count signal when an input pulse width exceeds a predetermined maximum time period. The input pulses and the minimum count signal are coupled as inputs to a latching circuit designed to provide temporary storage of a latching signal indicating that a minimum pulse width has been detected. The maximum count signal is coupled to a one-shot for providing a discard signal when the pulse width exceeds the predetermined maximum time period. The minimum pulse width latch signal is coupled via a load control latch to apply a timing signal to the serial input of a shift register which is clocked by a divided signal from the stable clock. The discard signal is coupled to reset the shift register and load control latch thereby rejecting the injected timing signal when the input pulse width exceeds the predetermined maximum width. In operation, the shift register will provide a delayed replica of the timing signal to appropriate decoding circuitry only when a pulse from the pulse train input falls within a predetermined range. This operation is performed for each pulse received by the counter so that the decoding circuitry only receives an indication when pulses of proper duration have been received.

It is therefore a feature of the invention to provide a simple, inexpensive and versatile technique for pulse width discrimination.

Another feature of the invention is to provide a digital pulse width detecting circuit which may be implemented with conventional technology.

A further feature of the invention is to provide a pulse width discriminating circuit which uses a digital counter to detect minimum and maximum pulse width.

Still another feature of the invention is to provide a pulse width discrimination and decoding circuit which provides decoding only when pulses falling within a predetermined timing window have been received.

Yet another feature of the invention is to provide a pulse width discriminating circuit which includes a counter and shift register for initiating a timing window upon receipt of a minimum pulse width input and for discarding the timing window if the pulse width exceeds a maximum limit.

A still further feature of the invention is to provide a digital decoding circuit which is stable in operation and insensitive to timing drifts for accurately decoding a series of pulses of predetermined width.

These and other advantages and novel features of the invention will become apparent from the following detailed description when considered with the accompanying drawing wherein:

BRIEF DESCRIPTION OF THE DRAWING

The FIGURE shows a schematic diagram of the circuit representing the pulse width discriminator and decoder in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the drawing, there is shown a pulse width discriminator and decoding circuit 10 in accordance with the present invention. In the present example, the description of the circuit and its operation will be made in connection with its use as part of an air traffic control (ATC) transponder. It will be understood, however, that the disclosed circuits are not restricted to avionics or similar systems but may be used in a variety of other equipments where it is desired to provide pulse width discrimination and signal decoding.

As is generally known, an ATC transponder is an instrument employed in an aircraft to automatically provide certain messages to an air traffic control center during flight in a particular geographic area. The transponders may be constructed in a variety of configurations but their primary function is to transmit specific information to the air traffic control center in response to interrogation pulses from the air traffic control center. The information, for example, may be an aircraft identification number or aircraft elevation data needed by the air traffic control center for proper flight coordination. Furthermore, aircraft location can be determined from the reply transmission. The transponders operate in response to the interrogation pulses transmitted by the air traffic control center when they are within the controlled area. Interrogations are transmitted with a coded format and formed to have pulse widths within a predetermined range. By way of example, in a given time period, the pulses may be time coded to elicit a first response by a receiving aircraft when a certain spacing of pulses is received and elicit a second response by the receiving aircraft when another spacing of pulses is received. Variations of the timing of the pulses can be made in any manner to obtain numerous responses for furnishing the required information from the interrogated aircraft.

In order to respond to the interrogation pulses transmitted by the air traffic control center, an aircraft must include receiving circuitry capable of detecting and decoding the series of transmitted pulses provided by the air traffic control center. After the pulses are detected and decoded, specific circuitry generates a response which causes the aircraft to automatically transmit the information requested by the coded pulsed interrogations. The information is transmitted each time a proper interrogation is made, thereby continuously providing the air traffic control center with up-dated information. In this manner, the control center may monitor any number of aircraft within its vicinity merely by transmitting appropriate interrogation signals to obtain specific information from those aircraft.

In the operation of the above system, it can be appreciated that proper responses from an interrogated aircraft are only transmitted if the aircraft receiving circuitry accurately receives, detects, and decodes the interrogation pulses. An important part of the detection technique requires the receiving system to be capable of distinguishing between interrogation pulses and other electromagnetic pulses caused by unwanted or spurious sources. Such unwanted signals can cause needless transponder operation as well as inhibit proper transponder response to interrogation signals. Accordingly, in order to more easily identify the interrogation pulses, they are generally transmitted with a pulse width falling within a predetermined range of values. Since the pulse width range is the standard, any pulses formed by spurious signals and falling outside of the predetermined range are rejected by the receiving circuitry. As was previously noted, the prior art normally accomplishes such discrimination in pulse widths by employing lumped delay lines or analog delays to compare pulse widths. However, their bulkiness makes the unsuitable and undesirable for use with the current technology of miniaturized and integrated circuits. In addition, electrical drifts in analog delays require numerous undesirable adjustments for proper operation. In current aircraft systems, such circuits take up more room, are more expensive to construct, are more complex in operation and require more repair and adjustment time than is acceptable for flight conditions.

In accordance with the present invention, a digital pulse width discriminator and decoder is constructed which is compatible with current miniaturized high-speed integrated circuit technology and accurately detects and decodes pulses having a width falling within a predetermined range. In the drawing, the discriminator and decoder 10 includes input terminal 12 which receives a train of input pulses, such as ATC interrogation pulses. The input 12 may be coupled to receive such pulses from any conventional aircraft receiving circuitry, the details of which are unimportant to the description of the present invention. The signal at input 12 is coupled over line 14 as one input to a reset terminal R of counter 16. The signal input from 12 is also coupled over line 18 to a reset terminal R of latch circuit 20. The counter 16 may be of any conventional construction and may typically be a digital counter wherein the signal from 12 is coupled to the counter to enable the counter 16 on the leading edge of a pulse input to terminal 12. The counter 16 is designed to have a clock input C which responds to a clock signal from clock 22 causing the counter to count as long as there is a pulse input at terminal 12. In the present example, the counter 16 counts in response to digital pulses received from clock 22 over line 24. In the description which follows, the signals will be described with reference to the use of conventional "zero" and "one" logic levels, although it will be understood that any logic level or combination of levels could be used as long as the described functional cooperation is obtained.

Normally, the pulse input received from terminal 12 is preconditioned in a conventional manner to provide a voltage pulse of predetermined magnitude representing a logic zero. Clock 22 is likewise constructed to provide a series of clock pulses represented by alternating periods of logic ones and zeros, which when coupled over line 24 to counter 16, cause the counter to count as long as a pulse is present on line 14. Two output signals are taken from the counter 16 on lines 26 and 28. The output signal from line 26 is normally a logic zero until the count reaches a predetermined minimum count (representing a time period corresponding to a minimum desired pulse width) when it changes to a logic one. Thus, after receipt of an input pulse at terminal 12, the counter 16 counts and provides an output signal on line 26 if the pulse remains as input to terminal 12 until the counter 16 reaches the minimum count. In the same manner, the output signal on line 28 is normally a logic zero until the count reaches a predetermined maximum count (representing a time corresonding to a maximum desired pulse width) when it changes to a logic one. Again, the counter will only provide an output signal on line 28 if the pulse input to terminal 12 remains until the count has reached the maximum count. In both cases, if a pulse input from 12 is not maintained on line 14 to the counter 16 until the count for each of the outputs 26 and 28 has been reached, there will be no signal output from line 26 or 28. Additionally, when the pulse input to 12 terminates, the counter 16 resets to zero and the latch 20 also resets to zero.

The minimum count signal from counter 16 is provided over line 26 to latch 20 as shown in the drawing. The latch 20 is constructed as a conventional digital logic circuit wherein the input pulse at terminal 12 is coupled through line 18 to the reset input R of the latch. In this example, during the absence of an input pulse, a logic one (high level) signal resets the latch and causes a zero logic output signal (logic low) on line 30 of the latch 20. The latch 20 is constructed to reset on the trailing edge of a pulse input to terminal 12 and resets each time a pulse terminates at the input terminal 12. The output line 26 from counter 16 is coupled to the set input S of the latch 20. Again the latch 20 is constructed to provide a logic high output on line 30 on the leading edge of a logic high output from line 26. The output line 30 is in turn coupled through lines 32 and 34 to load control 36 and decoder 38 respectively, the operation of which will be subsequently described.

The signal from clock 22 which is provided over line 24 to counter 16, is also provided over line 40 to divider 42 and thence over line 44 to the clock input of a shift register 46. The divider 42 is constructed to be, for example, a divide-by-ten reduction of the clock waveform from clock 22 and operates to clock shift register 46 at a reduced clock speed. The shift register 46 may be of any conventional construction and may include a plurality of multi-bit shift registers serially coupled to provide the required pulse storage and shifting. Such shift registers are constructed so that when a bit (logic high or low) of information is inserted into a first position, it will be shifted one position with each succeeding clock pulse along the length of the register unless the register is reset. When the register is reset, all bit positions are cleared and placed at the same logic level. In the present example, the shift register is configured initially, and upon reset, to have all logic low level signals in its bit positions. The entry of logic high or low signals into the register 46 is then determined by the logic level of the output on line 48 from load control 36. Thus, when a logic high output from load control 36 appears as input to the shift register 46, a logic high level will be read into the first bit position of the register 46 and, on each succeeding clock pulse, will be shifted successively along the length of the register 16. Similarly, when a logic low signal output from load control 36 appears as input to the shift register 46, a logic low level will be read into the first bit position and shifted successively along the length of the register 16 on each succeeding clock pulse from 44.

In the present example, the output from latch 20 is coupled over line 32 to the load control 36 so that a logic high is delivered as input to the load control 36 when a logic high is received by latch 20 over line 26. When this occurs, the load control 36 is designed to provide a logic high as an output which is coupled over line 48 to the input of the shift register 46 and which remains there until the load control 36 is reset. The load control 36 may be constructed as a conventional flip-flop latch circuit wherein a logic high received on line 32 causes a logic high on the output line 48 and a logic high received at reset input R of load control 36 causes the output on line 48 to go to a logic low. In the circuit shown, the signal input to input R of load contraol 36 is provided over line 50 from an output of shift register 46 or one-shot 54. The signal output on line 50 from the shift register 46 may be taken from any one of the shift register outputs which provides a logic high after a predetermined number of shifts following the receipt of a logic high signal over line 48. The effect of this operation is to cause the entry of a timing pulse (signal) in the shift register 46 which has a width proportional to the number of positions represented by the output on line 50. The timing pulse thus entered will be shifted along the register unless a logic high signal is received at the input to the reset R of shift register 46 at which time all bit positions will be reset to a logic low.

The output of the shift register 46 is provided over line 52 and may be selected from any number of bit positions representing a predetermined time period after entry of the timing pulse over line 48. The output logic signal is coupled through line 52 to the decoding circuit 38. The maximum count signal from line 28 representing maximum pulse width, is coupled to a conventional one-shot 54 and thence over line 56 to the reset input R of shift register 46 and through OR-gate 57 to the reset R of load control 36. As is known, the oneshot 54 provides a pulse output of limited duration representing a logic high level upon receipt of a logic high on line 28. This logic high output on line 56 acts as a discard signal and discards the timing pulse entered in shift register 46 by resetting all bit positions (shift register outputs) to zero.

The decoder 38 is designed to provide an output when the proper interrogation pulses have been received. Thus, coincidence of the signal on line 34 indicating the presence of a pulse of minimum width, and the delayed timing signal of line 52 indicates a valid interrogation within the appropriate range of pulse spacing. The decoder will then elicit the response that should be made. The response on output line 58 may be provided to other circuitry for transmitting the appropriate information. The structure of the decoder 38 is not critical to the operation of the present invention and may include any logic circuits capable of decoding the timing arrangement of pulses received at 12 during the timing window provided by the output from line 52 in order to decipher the transmitted code. Such circuits are well known in the prior art and a further detailed description is unnecessary to a proper understanding of the operation of the present invention.

The operation of the circuit is readily apparent when considered in connection with the receipt of a pulse at the input terminal 12. The leading edge of a pulse received at input 12 will enable counter 16 over line 14. At the same time, clock 22 will be delivering clock pulses at a predetermined frequency to the clock input C of counter 16, thereby causing counter 16 to increment its count outputs. If the input pulse to terminal 12 is not an interrogation pulse and does not have a pulse width sufficient to remain as an input to the reset input R of counter 16 until the minimum count is reached and a signal generated at output 26, the input to line 12 will disappear and the counter 16 will be reset to zero and cease to count. As a result, no logic high signal will appear at the output 26 and no further action of the discrimination circuit will occur.

If, however, the input pulse at 12 has a width which exceeds a predetermined minimum value, the counter 16 will provide a logic high signal on line 26, provided the input pulse remains on line 14. At this time, the latch 20, which was reset by the falling edge of the pulse at 12, will be set by the output on line 26 and thus provide a logic high signal at its output to line 30. The signal at output 30 will be transmitted over line 32 and 34 to the load control 36 and decoder 38, respectively, and will remain on those lines until the latch 20 is reset by the termination of the input pulse at 12. The load control 36, upon receipt of a logic high signal on line 32, will provide a logic high signal on line 48. The signal will remain on line 48 until a logic high signal is received over line 50 to reset the load control 36. The clock 22, through divider 42, will cause the shift register 46 to shift the timing pulse input from line 48 along the shift register 46 at a rate determined by the clock frequency. After a first predetermined time, the timing pulse will arrive at output line 50 and a logic high signal will be delivered over line 50 to reset load control 36 and remove the logic high signal on line 48. The timing pulse thus stored in the shift register 46 will then be successively moved along the shift register as each clock pulse is received from divider 42.

If the input pulse at 12 is a proper interrogation pulse having a pulse width falling within the predetermined range (fixed by minimum and maximum count outputs 26 and 28), the signal at input 12 will stay on line 14 until a logic high signal output is provided on line 26, but disappear on line 14 before the counter reaches the maximum count required to provide a logic high signal output on line 28. Thus, the shift register 46 will continue to shift the timing pulse along the register until it appears as output on line 52. The timing of the shift register 46 and counter 16, as controlled by clock 22 and divider 42, is such that the output signal on line 52 produces a timing window for enabling pulse decoding in conjunction with the signal from latch 20 on line 34. If the proper number of successive pulses arrive in the appropriate timed relation at the input 12, the decoder 38 provides an output indicative of the detected code. If, however, pulses of proper width are received but are not properly timed, the decoder 38 will fail to provide an output on line 58 and the aircraft will not respond to the interrogation.

If the input to terminal 12 is a pulse which has a width greater than the predetermined value, it will remain at input terminal 12 at least until the counter 16 reaches the maximum count and provides a logic high signal on line 28. At that time, the one-shot 54 will receive that signal and cause the generation of a discard signal over line 56 to reset shift register 46 and load control 36. This will cause the shift register 46 to reset to its initial value and essentially discard any timing pulse that was entered at 48 before it can create a timing window output over line 52. Another timing pulse will not be entered into the shift register 46 until the latch 20 is set by the signal from line 26 indicating the presence of another input pulse at 12 having a minimum required width.

As can be seen from the above description, the pulse width discriminator and decoding circuit enables the simple and inexpensive discrimination of pulses by digitally detecting minimum and maximum pulse widths. If a pulse input falls within a predetermined range as determined by the outputs from counter 16, appropriate signals are provided to enable proper operation of decoding circuitry. If the pulse is of insufficient width, the timing window over line 52 is never generated and the decoder 38 does not provide a signal from output 58 to generate a response to the pulse. Likewise, if the pulse on line 12 is of greater than allowed width, the output from line 28 through one-shot 54 resets the shift register to prevent the timing window from appearing on line 52 and again prevent decoding by circuit 38. In this manner, the circuit is capable of discriminating against numerous spurious pulses which may have widths falling outside a selected range of pulse widths. The circuit thus prevents responses to spurious pulses and interrogation pulses of other than the proper interrogation pulse width. The digital nature of each of the circuit elements enables highly accurate and reproducible timing of element operation and, when used in connection with the highly accurate clock 22, enables accurate control with miniaturized circuits requiring little or no adjustment during equipment lifetime. The circuits can be easily deposited using integrated circuit technology and are compatible with a wide variety of instruments requiring pulse width discrimination.

In one embodiment of the invention, the clock 22 was constructed as a crystal-driven oscillator operated at 27.586 MHz. The divider was a divide-by-ten and the counter 16 was coupled to provide a minimum count output on line 26 at 12 or 0.435 microseconds and a maximum count output on line 28 at 32 or 1.16 microseconds. The interrogation pulses normally have a nominal width of 0.8 microseconds. As thus constructed, the circuit was capable of providing a rejection of pulses having widths generally less than 0.3 microseconds and greater than 1.5 microseconds.

Although the invention has been described with reference to particular elements, it is to be understood that other equivalent circuit elements could be used to accomplish similar functions. Likewise, although reference has been made throughout to specific zero and one logic levels and the control exercised by those levels, it is evident that the levels could be reversed or interchanged in a variety of ways to perform the same functions described with respect to the discriminator circuit 10. Obviously many other modifications and variations are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described. 

What is claimed is:
 1. A pulse discriminating apparatus comprising:means for receiving an input pulse and providing a first signal when said input pulse width exceeds a predetermined minimum time period and providing a second signal when said input pulse width exceeds a predetermined maximum time period; and timing means responsive to said input pulse and said first signal for providing a timing signal output when said input pulse width exceeds said predetermined minimum time period and responsive to said second signal for discarding said timing signal and preventing a timing signal output when said input pulse width exceeds said predetermined maximum time period, said timing means providing said timing signal output only when said input pulse width falls in a range between said minimum and said maximum predetermined time periods.
 2. A pulse width discriminating apparatus.comprising:means for receiving an input pulse and providing a first signal when said input pulse width exceeds a minimum time period and providing a second signal when said input pulse width exceeds a maximum time period; means responsive to said first signal and said input pulse for providing a timing signal; and means coupled to receive said timing signal for providing said timing signal as an output when said input pulse width exceeds a predetermined minimum time period and responsive to said second signal for discarding said timing signal to prevent an output of said timing signal when said input pulse width exceeds a predetermined maximum time period.
 3. The apparatus of claim 2 wherein said means for receiving said input pulse comprises a digital counter constructed to be enabled upon receipt of the leading edge of an input pulse and which incrementally counts during the presence of an input pulse, said first signal being provided as a minimum count signal when said pulse remains as input to said counter for a time exceeding a predetermined minimum time period and said second signal being provided as a maximum count signal when said input pulse remains as input to said counter for a time exceeding a predetermined maximum time period.
 4. The apparatus of claim 2 wherein said means for providing a timing signal includes:a digital latch circuit coupled to receive said input pulse and said first signal and provide a latch signal when said input pulse and said first signal are concurrently present at said latch; and control means responsive to said latch signal for providing said timing signal.
 5. The apparatus of claim 4 wherein said control means has an input, an output and a reset terminal, said control input terminal being coupled to receive said latch signal and provide said timing signal in response thereto and said control reset terminal being constructed to remove said timing signal in response to a reset signal.
 6. A pulse width discriminating apparatus comprising:means for receiving an input pulse and providing a first signal when said input width exceeds a predetermined minimum time period and providing a second signal when said input pulse width exceeds a predetermined maximum time period, said means for receiving said input pulse comprising a digital counter constructed to be enabled upon receipt of a leading edge of an input pulse and which incrementally counts during the presence of an input pulse, said first signal being provided as a minimum count signal when said pulse remains as input to said counter for a time exceeding a predetermined minimum time period and said second signal being provided as a maximum count signal when said input pulse remains as input to said counter for a time exceeding a predetermined maximum time period; means responsive to said first signal and said input pulse for providing a timing signal and including a digital latch circuit coupled to receive said input pulse and said first signal and provide a latch signal when said input pulse and said first signal are concurrently present at said latch and control means responsive to said latch signal for providing said timing signal, said control means having an input, an output and a reset terminal, said control means input terminal being coupled to receive said latch signal and provide said timing signal in response thereto and said control means reset terminal being constructed to remove said timing signal in response to a reset signal; and means coupled to receive said timing signal for providing said timing signal as an output when said input pulse width exceeds a predetermined minimum time period and responsive to said second signal for discarding said timing signal to prevent an output of said timing signal when said input pulse width exceeds a predetermined maximum time period, said means for receiving said timing signal including a shift register coupled to receive and shift said timing signal along said register, said shift register providing a reset signal to said control means reset terminal a first predetermined time after receipt of a timing signal and providing said timing signal as an output a second predetermined time after receipt of said timing signal, said register being responsive to a reset signal for preventing timing signal output when the width of said input pulse exceeds said predetermined maximum time period.
 7. The apparatus of claim 6 wherein said means for receiving said timing signal further includes a one-shot circuit coupled to receive said maximum count signal and provide a discard signal as the reset signal to said shift register and said control means when said input pulse exceeds a predetermined maximum time period.
 8. The apparatus of claim 7 further including a decoding means coupled to receive said latch signal and said timing signal for providing a decoding output when said input pulse width falls within a range between said minimum and maximum time periods.
 9. A pulse width discriminating apparatus comprising:clock means for providing a train of clock pulses; counter means for receiving an input pulse and responsive to said clock means during the presence of an input pulse for providing a first minimum count signal when said input pulse width exceeds a predetermined minimum width and for providing a maximum count signal when the said input pulse width exceeds a predetermined maximum width; latch means coupled to said counter means and responsive to the simultaneous presence of an input pulse and said first signal for providing a latch signal; one-shot means coupled to said counter means and responsive to said second signal for providing a discard signal; load control means coupled to said latch means and responsive to a latch signal for providing a timing signal, said load control means having a reset terminal for removing said timing signal upon receipt of a reset signal; and shift register means coupled to said clock means, load control means and one-shot means for receiving said timing signal and shifting said timing signal along said register in response to a train of clock pulses, said shift register providing a reset signal to said load control reset terminal a first predetermined time period after receipt of said timing signal and providing said timing signal as an output a second predetermined time period after receipt of said timing signal, said shift register including a reset input coupled to said one-shot means and responsive to said discard signal for preventing said timing signal output.
 10. The apparatus of claim 9 further including a divider means coupled to receive a signal from said clock means and provide a divided clock train for clocking said shift register means. 